(1) Field of the Invention
This invention relates to an apparatus and method of fabrication used for semiconductor integrated circuit devices, and more specifically to an improved apparatus and process for post chemical-mechanical polishing (CMP) cleaning.
(2) Description of Related Art
Chemical-mechanical polishing (CMP) has been developed for providing smooth planar topographies on surfaces deposited on semiconductor substrates. For example, rough topography results when metal conductor lines are formed over a substrate containing device circuitry. The metal conductor lines serve to interconnect discrete devices, and thus form integrated circuits. The metal conductor lines are further insulated from the next interconnection level by layers of insulating material and holes formed through the insulating layers provide electrical access between successive conductive interconnection layers. In such wiring processes, it is desirable that the insulating layers have a smooth surface topography, since it is difficult to lithographically image and pattern layers applied to rough surfaces. CMP can, also, be used to remove different layers of material from the surface of a semiconductor substrate. For example, following via hole formation in an insulating material layer, a metallization layer is blanket deposited and then CMP is used to produce planar metal studs.
Briefly, the CMP processes involve holding and rotating a thin, flat substrate of the semiconductor material against a wetted polishing surface under controlled chemical, pressure and temperature conditions. A chemical slurry containing a polishing agent, such as alumina or silica, is used as the abrasive material. In addition, the chemical slurry contains selected chemicals which etch various surfaces of the substrate during processing. The combination of mechanical and chemical removal of material during polishing results in superior planarization of the polished surface.
The CMP process leaves a contaminant layer on the surfaces of the semiconductor substrate. This contaminant layer comprises substantially abrasive particles from the polishing slurry and may consist of alumina or silica particles saturated with chemicals added to the polishing slurry. In addition, the contaminant layer may comprise reaction products of the polishing slurry and the polished surfaces. It is necessary to remove the contaminant layer prior to subsequent processing of the semiconductor substrate in order to avoid degradation in device reliability and introduction of defects which reduce the manufacturing process yield.
U.S. Pat. No. 5,442,828 entitled "Double-Sided Wafer Scrubber With a Wet Submersing Silicon Wafer Indexer" granted Aug. 22, 1995 to Rick A. Lutz describes a wet indexer apparatus, including a tank for pre-soaking semiconductor wafer substrates in a solution before transferring the wafer substrates to a subsequent processing operation.
U.S. Pat. No. 5,478,436 entitled "Selective Cleaning Process For Fabricating a Semiconductor Device" granted Dec. 26, 1995 to Paul M. Winebarger et al describes a post-CMP cleaning process for semiconductor substrates in which a solution of an organic solvent and a fluorine containing compound removes metal contaminants from the suface of the semiconductor substrates.
While these inventions result in improvements to the CMP process they do not address overall manufacturing concerns, and therefore do not provide an effective, low-cost, high throughput post-CMP cleaning process.
The present invention is directed to a novel and improved apparatus and method for post chemical-mechanical polishing (CMP) cleaning.